In a conventional data transmission between LSIs, source synchronous transmission scheme has been used to achieve high-speed and high-response data transmission. FIG. 9 is a block diagram showing an example of a configuration of a conventional inter-LSI transmission system. The inter-LSI transmission system of FIG. 9 includes one transmitter LSI 101 and two receiver LSIs 102a and 102b. The receiver LSIs 102a and 102b have the same configuration. Transmission paths between the transmitter LSI 101 and receiver LSIs 102a, 102b including a clock transmission path for transmitting a source clock and a data transmission path for transmitting transmission data are bundled into one for transmission over the same path length.
A transmitter LSI system clock is input to the transmitter LSI 101 from outside. A receiver LSI system clock is input to the receiver LSIs 102a and 102b from outside. Further, an inter-LSI sync signal is input respectively to the transmitter LSI 101 and two receiver LSIs 102a and 102b from outside.
It is to be noted, in such an inter-LSI transmission system, that the transmission delay time changes depending on the length of an inter-LSI transmission path. In the case where data transmission from the LSI 101 to LSI 102a and data transmission from LSI 101 to LSI 102b are performed, it is difficult to synchronize the timing at which the data can be referred to on the LSI 102a and LSI 102b. To that end, it has been necessary to deliver a kind of a definer signal serving as a reference signal to both the LSIs 102a and 102b from outside.
As a prior art relating to the present invention, Patent Document 1 described below is known.
Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 2001-195354 (Pages 3 to 5, FIG. 1)
In the technique disclosed in Patent Document 1, synchronization is established at the initial clock of the source clock signal from the transmitter LSI 101 in order to determine the timing at which the data can be referred to on the LSI 102a and LSI 102b. The initial waveform in high frequency data transmission is generally bad in quality, so that performing synchronization using only the initial clock may decrease reliability.
Further, in order to establish resynchronization after initialization of only the receiver LSI, it has been necessary to define/design the definer signals corresponding to the number of types of interfaces and to provide independent resets for each interface.